- Industry’s first commercial integration of OTS selector with oxide-based ReRAM
- Key technology milestone achieved three months ahead of schedule
HOD HASHARON, Israel, June 24, 2021 (GLOBE NEWSWIRE) — Weebit Nano Limited (ASX:WBT), a leading developer of next-generation semiconductor memory technologies, is pleased to announce it has created the industry’s first commercial integration of an oxide-based ReRAM (OxRAM) cell with an ovonic threshold switching (OTS) selector, a critical step in the company’s commercialisation path for the discrete (stand-alone) memory market.
This achievement is a significant step towards broadening Weebit’s target market beyond embedded non-volatile memory (NVM) to include discrete memory technology, and will enable the implementation of 3D memory stacking and crossbar architectures in future developments. Weebit and its development partner CEA-Leti achieved this key milestone three months ahead of Weebit’s previously announced schedule.
A selector is a key element of a memory chip, enabling optimised cell access within a memory array. It assists in isolating memory cells so only the specific cells that should be accessed are, and all the other cells are not impacted. In the embedded space, a transistor is typically used as the selector device, but a transistor does not support the densities required for discrete chips. OTS is an ideal selector technology for discrete ReRAM chips as it enables the smallest ReRAM bit cell, as small as 4F2, as well as excellent endurance, low energy consumption, and high switching speed.
“New markets like IoT, 5G and AI are driving needs for emerging NVM on advanced process nodes,” said Jim Handy, Memory Analyst, Objective Analysis. “Weebit’s combination of ReRAM with an OTS selector promises to scale to the advanced processes and high memory densities that new memory chips will need.”
According to Gabriel Molas, Senior Scientist at CEA-Leti, “Creation of an OTS selector is quite a complex endeavor given the concurrent requirements to achieve high endurance, reduce variability, and maintain characteristics at high temperature operation. As such, this selector is based on several years of research by a dedicated team. We’re delighted to have worked with Weebit to achieve this milestone for its ReRAM technology more quickly than anticipated, and we look forward to continuing our joint R&D work with Weebit on further innovations.”
Coby Hanoch, CEO of Weebit, said, “This achievement demonstrates our commitment to addressing the discrete memory market as part of our mid-term strategy. We see a broad range of opportunities for discrete ReRAM, from NOR flash to storage class memory, in a range of segments. Given our 2024 target for a discrete solution, we anticipate that other opportunities will arise as well. We will continue to share our progress in meeting this mid-term goal, while we continue our near-term focus on the embedded memory module where we are making good progress.”
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This announcement has been authorised for release by the Board of Weebit Nano.
About Weebit Nano
Weebit Nano Ltd. is a leading developer of next-generation semiconductor memory technology. The company’s ground-breaking Resistive RAM (ReRAM) addresses the growing need for significantly higher performance and lower power memory solutions in a range of new electronic products such as Internet of Things (IoT) devices, smartphones, robotics, autonomous vehicles, 5G communications and artificial intelligence. Weebit’s ReRAM allows semiconductor memory elements to be significantly faster, less expensive, more reliable and more energy efficient than those using existing Flash memory solutions. Because it is based on fab-friendly materials, the technology can be quickly and easily integrated with existing flows and processes, without the need for special equipment or large investments. See: www.weebit-nano.com or follow us on https://twitter.com/WeebitNano.
Weebit Nano and the Weebit Nano logo are trademarks or registered trademarks of Weebit Nano Ltd. in the United States and other countries. Other company, product, and service names may be trademarks or service marks of others.
Explanation of Technical Terms
4F2: Memory cell sizes are measured using an nF² formula where ‘n’ is a constant derived from the cell design and ‘F’ is the feature size of the process technology. For example, in a 130nm process node, F = 0.13 micron, and therefore 4F2 = 4 x 0.13 x 013 = 0.0676 square micron. For the same feature size, as the cell size becomes smaller, memory capacity increases.
Bit cell: A bit cell is the basic building block of a memory array, and in turn, of a memory chip. Each cell comprises a tiny circuit with a memory element and a selector element. The memory element stores data (either a 1 or 0) and the selector activates the cell when accessed.
For further information please contact:
Eric Kuret, Market Eye
P: +61 417 311 335
E: [email protected]
P : +1 650-336-4222
E: [email protected]
A photo accompanying this announcement is available at https://www.globenewswire.com/NewsRoom/AttachmentNg/58ea20f0-1cab-4135-8b9d-62dfc0fd48f6
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